Programmable logic devices (PLDs), such as field programmable logic devices (FPGAs), are beneficial because they allow a user to implement a circuit designed for a specific product implementation based upon a user design at the choice of the user. However, FPGAs are generally not easy to debug. Depending on the use case, there are 2 main ways that FPGAs are typically debugged, in-system debug and prototype/emulation. There may an area of the FPGA logic that needs to be debugged because it is not working as expected. In this use case, it may be beneficial to perform in-system debug by using a software tool, such as ChipScope software available from Xilinx, Inc., to implement an Integrated Logic Analyzer (ILA) connected to the approximately 5% of signals that are selected to be monitored, perform place and route, and then interactively debug the design at system speeds. However, such an in-system debug approach is not possible for a product already in production without logic predefined.
Another debugging method includes prototype/emulation, which requires monitoring 100 percent of a design running on the FPGA. Because it may be too intrusive in terms of area and time to perform prototype and emulation of 100 percent of a design with ILA's, it may be necessary to advance the clock by one cycle, and then perform a chip read-back using a configuration network. After performing a read-back of the FPGA, it is them possible to advance the clock one cycle, and repeat. The effective “emulation” speed of the RTL on the FPGA is thus limited by this cycle of read-back followed by advancing the user clock.
Accordingly, circuits and methods that enable improved prototype/emulation of an FPGA are beneficial.